NXP Semiconductors /LPC18xx /SDMMC /CMD

Command index

Response expect

0 (NONE): None. No response expected from card

1 (EXPECTED): Expected. Response expected from card

Response length

0 (SHORT): Short. Short response expected from card

1 (LONG): Long. Long response expected from card

Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.

0 (DO_NOT_CHECK_RESPONS): Do not check response CRC

1 (CHECK_RESPONSE_CRC): Check response CRC

Data expected

0 (NONE): None. No data transfer expected (read/write)

1 (DATA): Data. Data transfer expected (read/write)

read/write. Don’t care if no data expected from card.

0 (READ_FROM_CARD): Read from card

1 (WRITE_TO_CARD): Write to card

Transfer mode. Don’t care if no data expected.

0 (BLOCK_DATA_TRANSFER): Block data transfer command

1 (STREAM_DATA_TRANSFER): Stream data transfer command

Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine: - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands - open-ended transfers that software should explicitly send to stop command Additionally, when resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don’t care if no data expected from card.

0 (NO_STOP_COMMAND_SENT): No stop command sent at end of data transfer

1 (SEND_STOP_COMMAND_AT): Send stop command at end of data transfer

Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command.

0 (SEND): Send. Send command at once, even if previous data transfer has not completed.

1 (WAIT): Wait. Wait for previous data transfer completion before sending command.

Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.

0 (DISABLED): Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0.

1 (ENABLED): Enabled. Stop or abort command intended to stop current data transfer in progress.

Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).

0 (NO): No. Do not send initialization sequence (80 clocks of 1) before sending this command.

1 (SEND): Send. Send initialization sequence before sending this command.

Reserved. Always write as 0.

Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.

0 (NORMAL): Normal. Normal command sequence

1 (NO): No. Do not send commands, just update clock register value into card clock domain

Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.

0 (NO_READ): No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device.

1 (READ): Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.

CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.

0 (DISABLED): Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device.

1 (ENABLED): Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device.

Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together.

Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card.

Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together.

Boot Mode

0 (MANDATORY_BOOT_OPERA): Mandatory Boot operation

1 (ALTERNATE_BOOT_OPERA): Alternate Boot operation

Voltage switch bit

0 (DISABLED): Disabled. No voltage switching

1 (ENABLED): Enabled. Voltage switching enabled; must be set for CMD11 only

Reserved

Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register.